1. Field of the Invention
This invention relates generally to electronic design automation (EDA) systems used for designing integrated circuits. The invention is more specifically related to a method and apparatus for monitoring the performance of a circuit optimization tool.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. Chip designers generally employ hierarchial design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip's functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a "behavior description"). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually are logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
It is useful to distinguish between those components of an integrated circuit design called cells, provided by a silicon chip vendor as primitive cells (i.e., leaf candidates), and the user-defined hierarchy blocks built upon them. One way is to speak of a "cell library" vs. a "design library" as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design. Initial cell library contents are usually provided by the chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term "NAND" for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND. When a 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip.
A single name is sufficient when dealing only in the context of a single user function. The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy may be a single block that defines the entire design, and the bottom layer of the hierarchy may consist of leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library. The resulting design is often called a detailed (or gate-level) description of the logic design.
The generation of the detailed description is often accomplished by logic design synthesis software for HDL entry. The logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors may be detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description.
The output of the design capture and synthesis tools is typically a logic design database which completely specifies the logical and functional relationships among the components of the design. Once the design has been converted into this form, it may be optimized by sending the logic design database to a logic optimizer tool typically implemented in software.
In many logic optimizer tools, the optimization process may include a characterization step, an optimization step, and a collection step. During the characterization step, various optimization parameters are assigned to selected portions of the design. For example, for those portions of the design that are to be optimized for timing, the characterization step may perform a timing analysis of the design, and identify critical paths within the design that need to be improved by optimization. The characterization step may then assign timing constraints to those portions of the design, indicating the degree that they must be optimized to meet the desired timing goals. Because of the size of many designs, the characterization step typically may only operate on one module of the design at any given time. As such, the characterization step may assign timing constraints to the selected module, based upon the circuitry interfacing therewith. The module that the tools is currently operating on may be termed the local or selected module, while all other modules may be termed remote modules.
After the characterization step is complete, the optimizer tool may perform an optimization step. The optimization step typically attempts to optimize the design such that all of the timing constraints assigned by the characterization step are satisfied. During the optimization step, the logic optimizer may, for example, remove logic from the design that is unnecessary, minimize the logic that is necessary to implement certain functions, increase the power of selected cells to improve performance, etc. Like the characterization step, the optimization step typically may only operate on one module of the design at any given time.
After all of the modules within the circuit design have been optimized, a collection step is typically executed. The collection step may collect the various optimized modules, and write the optimized modules into a single design file.
After the design has been optimized, the circuit designer typically verifies that the resulting logic definition is correct and that the integrated circuit implements the expected function. This verification is currently achieved by timing and simulation software tools. That is, the design is simulated to assess the functionality and timing of the design. If timing errors are found or the resulting functionality, is unacceptable, the designer modifies the behavior description as needed. This may help to ensure that the design satisfies the desired requirements.
After timing verifications and functional simulation have been completed, placement and routing of the design's components is performed. These steps involve allocating components of the design to locations on the integrated circuit chip and interconnecting the components to form nets. Finally, final timing verification is performed after placement and routing is complete.
A limitation of typical logic optimizer tools is that the performance of the optimization process cannot be monitored by the circuit designer. Often a small subset of the circuit modules may consume an inordinate amount of processing time to characterize and/or optimize. More particularly, certain characterization and/or optimization commands or steps may consume an inordinate amount of processing time. This may be caused for any number of reasons. For example, modules that have a large number of hierarchical levels can take much more processing time than modules that have less levels of hierarchy, and the bulk of the processing time may be consumed performing one specific characterization and/or optimization task.
Often there are ways to circumvent performance related problems once brought to the attention of the circuit designer. However, because typical logic optimizer tools do not provide a way to monitor the performance of the circuit optimization process, the performance related problems may not be detected, and thus corrected. This may substantially increase the overall time and cost required to perform the circuit optimization process, particularly for large circuit designs.